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<instructionsection id="MSR_r" title="MSR (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MSR" />
  </docvars>
  <heading>MSR (register)</heading>
  <desc>
    <brief>
      <para>Move general-purpose register to Special register</para>
    </brief>
    <authored>
      <para>Move general-purpose register to Special register moves selected bits of a general-purpose register to the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref> or <xref linkend="CHDDAABB">SPSR</xref>_&lt;current_mode&gt;.</para>
      <para>Because of the Do-Not-Modify nature of its reserved bits, a read-modify-write sequence is normally required when the <instruction>MSR</instruction> instruction is being used at Application level and its destination is not <value>APSR_nzcvq</value> (<value>CPSR_f</value>).</para>
      <para>If an <instruction>MSR</instruction> (register) moves selected bits of an immediate value to the <xref linkend="CIHJBHJA">CPSR</xref>, the PE checks whether the value being written to <xref linkend="BEIDIGBH">PSTATE</xref>.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
      <para>An <instruction>MSR</instruction> (register) executed in User mode:</para>
      <list type="unordered">
        <listitem><content>Is <arm-defined-word>unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</content></listitem>
        <listitem><content>Otherwise, does not update any <xref linkend="CIHJBHJA">CPSR</xref> field that is accessible only at EL1 or higher.</content></listitem>
      </list>
      <para>An <instruction>MSR</instruction> (register) executed in System mode is <arm-defined-word>unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</para>
      <para>The <xref linkend="CIHJBHJA">CPSR</xref>.E bit is writable from any mode using an <instruction>MSR</instruction> instruction.  Arm deprecates using this to change its value.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MSR_r/A1_AS.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="mask" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="m" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MSR_r_A1_AS" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of:&#10;* {value{APSR_&lt;bits&gt;}}">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_r/A1_AS.txt" mylink="aarch32.instrs.MSR_r.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');
if mask == '0000' then UNPREDICTABLE;
if n == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">mask == '0000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MSR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MSR_r/T1_AS.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="R" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="mask" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="MSR_r_T1_AS" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MSR" />
        </docvars>
        <asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of:&#10;* {value{APSR_&lt;bits&gt;}}">&lt;spec_reg&gt;</a><text>, </text><a link="sa_rn" hover="General-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MSR_r/T1_AS.txt" mylink="aarch32.instrs.MSR_r.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  write_spsr = (R == '1');
if mask == '0000' then UNPREDICTABLE;
if n == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">mask == '0000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_spec_reg">&lt;spec_reg&gt;</symbol>
      <account encodedin="mask">
        <intro>
          <para>Is one of:</para>
          <list type="unordered">
            <listitem><content><value>APSR_&lt;bits&gt;</value>.</content></listitem>
            <listitem><content><value>CPSR_&lt;fields&gt;</value>.</content></listitem>
            <listitem><content><value>SPSR_&lt;fields&gt;</value>.</content></listitem>
          </list>
          <para>For CPSR and SPSR, &lt;fields&gt; is a sequence of one or more of the following:</para>
          <list type="param">
            <listitem>
              <param>c</param><content>mask&lt;0&gt; = '1' to enable writing of bits&lt;7:0&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>x</param><content>mask&lt;1&gt; = '1' to enable writing of bits&lt;15:8&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>s</param><content>mask&lt;2&gt; = '1' to enable writing of bits&lt;23:16&gt; of the destination PSR.</content>
            </listitem>
            <listitem>
              <param>f</param><content>mask&lt;3&gt; = '1' to enable writing of bits&lt;31:24&gt; of the destination PSR.</content>
            </listitem>
          </list>
          <para>For APSR, &lt;bits&gt; is one of <value>nzcvq</value>, <value>g</value>, or <value>nzcvqg</value>. These map to the following CPSR_&lt;fields&gt; values:</para>
          <list type="unordered">
            <listitem><content><value>APSR_nzcvq</value> is the same as <value>CPSR_f</value> (mask== '1000').</content></listitem>
            <listitem><content><value>APSR_g</value> is the same as <value>CPSR_s</value> (mask == '0100').</content></listitem>
            <listitem><content><value>APSR_nzcvqg</value> is the same as <value>CPSR_fs</value> (mask == '1100').</content></listitem>
          </list>
          <para>Arm recommends the <value>APSR_&lt;bits&gt;</value> forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">The Application Program Status Register, APSR</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MSR_r_A1_AS, MSR_r_T1_AS" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MSR_r/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    if write_spsr then
        if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then
            UNPREDICTABLE;
        else
            <a link="impl-aarch32.SPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)">SPSRWriteByInstr</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], mask);
    else
        // Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism
        <a link="impl-aarch32.CPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)">CPSRWriteByInstr</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n], mask);</pstext>
    </ps>
  </ps_section>
  <constrained_unpredictables ps_block="Operation">
    <cu_case>
      <cu_cause>
        <pstext mayhavelinks="1">write_spsr &amp;&amp; PSTATE.M IN {M32_User,M32_System}</pstext>
      </cu_cause>
      <cu_type constraint="Constraint_UNDEF" />
      <cu_type constraint="Constraint_NOP" />
    </cu_case>
  </constrained_unpredictables>
</instructionsection>
