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<instructionsection id="STLEXH" title="STLEXH -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STLEXH" />
  </docvars>
  <heading>STLEXH</heading>
  <desc>
    <brief>
      <para>Store-Release Exclusive Halfword</para>
    </brief>
    <authored>
      <para>Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
      <para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
      <para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>Aborts and alignment</para>
      <para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
      <list type="unordered">
        <listitem><content>Memory is not updated</content></listitem>
        <listitem><content><syntax>&lt;Rd&gt;</syntax> is not updated.</content></listitem>
      </list>
      <para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
      <list type="unordered">
        <listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
        <listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
      </list>
      <para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STLEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STLEXH/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" name="ex" settings="1">
          <c>1</c>
        </box>
        <box hibit="8" name="ord" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXH_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STLEXH" />
        </docvars>
        <asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXH/A1_A.txt" mylink="aarch32.instrs.STLEXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
if d == n || d == t then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d == t</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d == n</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STLEXH" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STLEXH/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rt2" settings="4">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="7" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" width="2" name="sz" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="STLEXH_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STLEXH" />
        </docvars>
        <asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STLEXH/T1_A.txt" mylink="aarch32.instrs.STLEXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
if d == n || d == t then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d == t</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d == n</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
          <list type="param">
            <listitem>
              <param>0</param><content>If the operation updates memory.</content>
            </listitem>
            <listitem>
              <param>1</param><content>If the operation fails to update memory.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STLEXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
    if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,2) then
        <a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;
        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);
    else
        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</pstext>
    </ps>
  </ps_section>
</instructionsection>
