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<instructionsection id="SVC" title="SVC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SVC" />
  </docvars>
  <heading>SVC</heading>
  <desc>
    <brief>
      <para>Supervisor Call</para>
    </brief>
    <authored>
      <para>Supervisor Call causes a Supervisor Call exception. For more information, see <xref linkend="CIHFBAIJ">Supervisor Call (SVC) exception</xref>.</para>
      <note>
        <para><instruction>SVC</instruction> was previously called <instruction>SWI</instruction>, Software Interrupt, and this name is still found in some documentation.</para>
      </note>
      <para>Software can use this instruction as a call to an operating system to provide a service.</para>
      <para>In the following cases, the Supervisor Call exception generated by the <instruction>SVC</instruction> instruction is taken to Hyp mode:</para>
      <list type="unordered">
        <listitem><content>If the <instruction>SVC</instruction> is executed in Hyp mode.</content></listitem>
        <listitem><content>If <xref linkend="AArch32.hcr">HCR</xref>.TGE is set to 1, and the <instruction>SVC</instruction> is executed in Non-secure User mode. For more information, see <xref linkend="BEIJJBDG">Supervisor Call exception, when HCR.TGE is set to 1</xref></content></listitem>
      </list>
      <para>In these cases, the <xref linkend="AArch32.hsr">HSR, Hyp Syndrome Register</xref> identifies that the exception entry was caused by a Supervisor Call exception, EC value <hexnumber>0x11</hexnumber>, see <xref linkend="BEIDBEAG">Use of the HSR</xref>. The immediate field in the <xref linkend="AArch32.hsr">HSR</xref>:</para>
      <list type="unordered">
        <listitem><content>If the <instruction>SVC</instruction> is unconditional:<list type="unordered"><listitem><content>For the T32 instruction, is the zero-extended value of the <field>imm8</field> field.</content></listitem><listitem><content>For the A32 instruction, is the least-significant 16 bits the <field>imm24</field> field.</content></listitem></list></content></listitem>
        <listitem><content>If the <instruction>SVC</instruction> is conditional, is <arm-defined-word>unknown</arm-defined-word>.</content></listitem>
      </list>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SVC/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="SVC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SVC" />
        </docvars>
        <asmtemplate><text>SVC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm_1" hover="24-bit unsigned immediate [0-16777215] (field &quot;imm24&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SVC/A1_A.txt" mylink="aarch32.instrs.SVC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm24, 32);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SVC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/SVC/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="S" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SVC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SVC" />
        </docvars>
        <asmtemplate><text>SVC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a>{#}</a><a link="sa_imm" hover="8-bit unsigned immediate [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SVC/T1_A.txt" mylink="aarch32.instrs.SVC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SVC_A1, SVC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_A1, SVC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_A1" symboldefcount="1">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm24">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is a 24-bit unsigned immediate, in the range 0 to 16777215, encoded in the "imm24" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm24 in software, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SVC_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field. This value is for assembly and disassembly only. SVC handlers in some systems interpret imm8 in software, for example to determine the required service.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SVC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="AArch32.CheckForSVCTrap.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckForSVCTrap(bits(16) immediate)">AArch32.CheckForSVCTrap</a>(imm32&lt;15:0&gt;);
    <a link="AArch32.CallSupervisor.1" file="shared_pseudocode.xml" hover="function: AArch32.CallSupervisor(bits(16) immediate_in)">AArch32.CallSupervisor</a>(imm32&lt;15:0&gt;);</pstext>
    </ps>
  </ps_section>
</instructionsection>
