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<instructionsection id="BL_i" title="BL, BLX (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>BL, BLX (immediate)</heading>
  <desc>
    <brief>
      <para>Branch with Link and optional Exchange (immediate)</para>
    </brief>
    <authored>
      <para>Branch with Link calls a subroutine at a PC-relative address, and setting LR to the return address.</para>
      <para>Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, setting LR to the return address, and changes the instruction set from A32 to T32, or from T32 to A32.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BL_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="H" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_A1" oneofinclass="1" oneof="4" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <asmtemplate><text>BL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_2" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/A1_A.txt" mylink="aarch32.instrs.BL_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:'00', 32);  targetInstrSet = <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BL_i/A2_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="H" usename="1">
          <c></c>
        </box>
        <box hibit="23" width="24" name="imm24" usename="1">
          <c colspan="24"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_A2" oneofinclass="1" oneof="4" label="A2">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_3" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/A2_A.txt" mylink="aarch32.instrs.BL_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:H:'0', 32);  targetInstrSet = <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BL" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BL_i/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="10" name="imm10" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>1</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="11" name="imm11" usename="1">
          <c colspan="11"></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_T1" oneofinclass="1" oneof="4" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <asmtemplate><text>BL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/T1_A.txt" mylink="aarch32.instrs.BL_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">I1 = NOT(J1 EOR S);  I2 = NOT(J2 EOR S);  imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10:imm11:'0', 32);
targetInstrSet = <a link="InstrSet_T32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_T32</a>;
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BLX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BL_i/T2_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="10" name="imm10H" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="13" name="J1" usename="1">
          <c></c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" name="J2" usename="1">
          <c></c>
        </box>
        <box hibit="10" width="10" name="imm10L" usename="1">
          <c colspan="10"></c>
        </box>
        <box hibit="0" name="H" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="BL_i_T2" oneofinclass="1" oneof="4" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <asmtemplate><text>BLX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_label_1" hover="The label of instruction that is to be branched to">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BL_i/T2_A.txt" mylink="aarch32.instrs.BL_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if H == '1' then UNDEFINED;
I1 = NOT(J1 EOR S);  I2 = NOT(J2 EOR S);  imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10H:imm10L:'00', 32);
targetInstrSet = <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>;
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BL_i_A1, BL_i_T1, BL_i_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>For encoding A1, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A2" symboldefcount="2">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A1, BL_i_A2, BL_i_T1, BL_i_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A1" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm24">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <intro>
          <para>For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>BL</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
          <para>Permitted offsets are multiples of 4 in the range –33554432 to 33554428.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_A2" symboldefcount="2">
      <symbol link="sa_label_3">&lt;label&gt;</symbol>
      <account encodedin="imm24:H">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding A2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>BLX</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are even numbers in the range –33554432 to 33554430.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_T1" symboldefcount="3">
      <symbol link="sa_label">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BL" />
        </docvars>
        <intro>
          <para>For encoding T1: the label of the instruction that is to be branched to.</para>
          <para>The assembler calculates the required value of the offset from the PC value of the <instruction>BL</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are even numbers in the range –16777216 to 16777214.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BL_i_T2" symboldefcount="4">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BLX" />
        </docvars>
        <intro>
          <para>For encoding T2: the label of the instruction that is to be branched to.</para>
          <para>The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>BLX</instruction> instruction to this label, then selects an encoding with <field>imm32</field> set to that offset.</para>
          <para>Permitted offsets are multiples of 4 in the range –16777216 to 16777212.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then
        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> - 4;
    else
        <a link="impl-aarch32.LR.write.none" file="shared_pseudocode.xml" hover="accessor: LR = bits(32) value">LR</a> = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>&lt;31:1&gt; : '1';
    bits(32) targetAddress;
    if targetInstrSet == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then
        targetAddress = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32;
    else
        targetAddress = <a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32;
    <a link="impl-aarch32.SelectInstrSet.1" file="shared_pseudocode.xml" hover="function: SelectInstrSet(InstrSet iset)">SelectInstrSet</a>(targetInstrSet);
    <a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(targetAddress, <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a>);</pstext>
    </ps>
  </ps_section>
</instructionsection>
