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<instructionsection id="PUSH_STMDB" title="PUSH (multiple registers) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="PUSH" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STM" />
  </docvars>
  <heading>PUSH (multiple registers)</heading>
  <desc>
    <brief>Push multiple registers to Stack</brief>
    <longer> stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data</longer>
  </desc>
  <aliasto refiform="stmdb.xml" iformid="STMDB">STMDB, STMFD</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="16" name="register_list" usename="1">
          <c colspan="16"></c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STMDB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_3" hover="List of two or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="stmdb.xml#STMDB_A1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_3" hover="List of two or more registers to be stored">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STM" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="opc" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1" psbits="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" name="P" usename="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="13" width="14" name="register_list" usename="1">
          <c colspan="14"></c>
        </box>
      </regdiagram>
      <encoding name="PUSH_STMDB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="alias_mnemonic" value="PUSH" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STM" />
        </docvars>
        <asmtemplate comment="All registers in R0-R7, LR"><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="stmdb.xml#STMDB_T1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> SP!, </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field &quot;register_list&quot;)">&lt;registers&gt;</a></asmtemplate>
          <aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(M:register_list) &gt; 1</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_A1" symboldefcount="1">
      <symbol link="sa_registers_3">&lt;registers&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
        </docvars>
        <intro>
          <para>For encoding A1: is a list of two or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>The SP and PC can be in the list. However:</para>
          <list type="unordered">
            <listitem><content>Arm deprecates the use of instructions that include the PC in the list.</content></listitem>
            <listitem><content>If the SP is in the list, and it is not the lowest-numbered register in the list, the instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the SP.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PUSH_STMDB_T1" symboldefcount="2">
      <symbol link="sa_registers_2">&lt;registers&gt;</symbol>
      <account encodedin="register_list">
        <docvars>
          <docvar key="armarmheading" value="T1" />
        </docvars>
        <intro>
          <para>For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
          <para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
