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<instructionsection id="VFMA_bf" title="VFMAB, VFMAT (BFloat16, vector) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMA" />
    <docvar key="simdvectorsize" value="quad" />
  </docvars>
  <heading>VFMAB, VFMAT (BFloat16, vector)</heading>
  <desc>
    <brief>
      <para>BFloat16 floating-point widening multiply-add long (vector)</para>
    </brief>
    <authored>
      <para>The Bfloat16 floating-point widening multiply-add long instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies and adds these values to the overlapping single-precision elements of the destination vector.</para>
      <para>Unlike other BFloat16 multiplication instructions, this performs a fused multiply-add, without intermediate rounding that uses the Round to Nearest rounding mode and can generate a floating-point exception that causes cumulative exception bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMA_bf/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_A1_Q" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bf/A1_A.txt" mylink="aarch32.instrs.VFMA_bf.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer elements = 128 DIV 32;
integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMA" />
        <docvar key="simdvectorsize" value="quad" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMA_bf/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="op1" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="op2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMA_bf_T1_Q" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field &quot;Q&quot;)">&lt;bt&gt;</a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMA_bf/T1_A.txt" mylink="aarch32.instrs.VFMA_bf.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer elements = 128 DIV 32;
integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_bt">&lt;bt&gt;</symbol>
      <definition encodedin="Q">
        <intro>Is the bottom or top element specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;bt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">B</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">T</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMA_bf/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];
bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];
bits(128) operand3 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];
bits(128) result;

for e = 0 to elements-1
    bits(32) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);
    bits(32) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);
    bits(32) addend = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
    <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(addend, element1, element2,
                                   <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());

<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
