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<instructionsection id="VLD3_a" title="VLD3 (single 3-element structure to all lanes) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD3" />
  </docvars>
  <heading>VLD3 (single 3-element structure to all lanes)</heading>
  <desc>
    <brief>
      <para>Load single 3-element structure and replicate to all lanes of three registers</para>
    </brief>
    <authored>
      <para>Load single 3-element structure and replicate to all lanes of three registers loads one 3-element structure from memory into all lanes of three registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGHGDDF">VLD3 (single 3-element structure to all lanes)</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Alignment</para>
      <para>Standard alignment rules apply, see <xref linkend="CHDIDCCI">Alignment support</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' || a == '1' then UNDEFINED;
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
inc = if T == '0' then 1 else 2;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d3 &gt; 31</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD3" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="N" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" name="T" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="a" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD3_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD3_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD3" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,UNDEFINED]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&amp;FP registers (field &quot;T&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' || a == '1' then UNDEFINED;
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
inc = if T == '0' then 1 else 2;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  d2 = d + inc;  d3 = d2 + inc;  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d3 &gt; 31 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d3 &gt; 31</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD3_a_A1_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_T1_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="T">
        <intro>
          <para>Is a list containing the 64-bit names of three SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+1&gt;[], &lt;Dd+2&gt;[] }</syntax></param><content>Single-spaced registers, encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;[], &lt;Dd+2&gt;[], &lt;Dd+4&gt;[] }</syntax></param><content>Double-spaced registers, encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD3_a_A1_postr, VLD3_a_T1_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD3_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
    constant integer esize = ebytes * 8;
    bits(esize) element1 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address, ebytes];
    bits(esize) element2 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];
    bits(esize) element3 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];

    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element1, 64 DIV esize);
    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element2, 64 DIV esize);
    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element3, 64 DIV esize);
    if wback then
        if register_index then
            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];
        else
            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 3*ebytes;</pstext>
    </ps>
  </ps_section>
</instructionsection>
