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<instructionsection id="VMOV_h" title="VMOV (between general-purpose register and half-precision) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VMOV" />
  </docvars>
  <heading>VMOV (between general-purpose register and half-precision)</heading>
  <desc>
    <brief>
      <para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&amp;FP register</para>
    </brief>
    <authored>
      <para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&amp;FP register.  This instruction transfers the value held in the bottom 16 bits of a 32-bit SIMD&amp;FP register to the bottom 16 bits of a general-purpose register, or the value held in the bottom 16 bits of a general-purpose register to the bottom 16 bits of a 32-bit SIMD&amp;FP register.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VMOV_h/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toh_A1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_h_A1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_h/A1_A.txt" mylink="aarch32.instrs.VMOV_h.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
if cond != '1110' then UNPREDICTABLE;
to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">cond != '1110'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VMOV" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VMOV_h/T1_A.txt">
        <box hibit="31" width="11" settings="11">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="2" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="1" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="0" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="VMOV_toh_T1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="from-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VMOV_h_T1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VMOV" />
          <docvar key="to-or-from-gp" value="to-gp" />
        </docvars>
        <box hibit="20" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{&lt;Sn&gt;}} will be transferred to or from (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_sn" hover="32-bit SIMD&amp;FP register to be transferred (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VMOV_h/T1_A.txt" mylink="aarch32.instrs.VMOV_h.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
to_arm_register = (op == '1');  t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">InITBlock()</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the general-purpose register that <syntax>&lt;Sn&gt;</syntax> will be transferred to or from, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP register to be transferred, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VMOV_h/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();  <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
    if to_arm_register then
        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;15:0&gt;;
    else
        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]&lt;15:0&gt;;</pstext>
    </ps>
  </ps_section>
</instructionsection>
