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<instructionsection id="SB" title="SB -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="SB" />
  </docvars>
  <heading>SB</heading>
  <desc>
    <brief>
      <para>Speculation Barrier</para>
    </brief>
    <authored>
      <para>Speculation Barrier is a barrier that controls speculation.</para>
      <para>The semantics of the Speculation Barrier are that the execution, until the barrier completes, of any instruction that appears later in the program order than the barrier:</para>
      <list type="unordered">
        <listitem><content>Cannot be performed speculatively to the extent that such speculation can be observed through side-channels as a result of control flow speculation or data value speculation.</content></listitem>
        <listitem><content>Can be speculatively executed as a result of predicting that a potentially exception generating instruction has not generated an exception.</content></listitem>
      </list>
      <para>In particular, any instruction that appears later in the program order than the barrier cannot cause a speculative allocation into any caching structure where the allocation of that entry could be indicative of any data value present in memory or in the registers.</para>
      <para>The SB instruction:</para>
      <list type="unordered">
        <listitem><content>Cannot be speculatively executed as a result of control flow speculation or data value speculation.</content></listitem>
        <listitem><content>Can be speculatively executed as a result of predicting that a potentially exception generating instruction has not generated an exception. The potentially exception generating instruction can complete once it is known not to be speculative, and all data values generated by instructions appearing in program order before the SB instruction have their predicted values confirmed.</content></listitem>
      </list>
      <para>When the prediction of the instruction stream is not informed by data taken from the register outputs of the speculative execution of instructions appearing in program order after an uncompleted SB instruction, the SB instruction has no effect on the use of prediction resources to predict the instruction stream that is being fetched.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="SB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_SB" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/SB/A1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="7" width="4" name="opcode" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SB_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SB" />
        </docvars>
        <asmtemplate><text>SB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SB/A1_A.txt" mylink="aarch32.instrs.SB.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">// No additional decoding required</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="SB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.5" feature="FEAT_SB" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/SB/T1_A.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" name="opc" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="option" settings="4">
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="SB_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SB" />
        </docvars>
        <asmtemplate><text>SB</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SB/T1_A.txt" mylink="aarch32.instrs.SB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SB_A1, SB_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="impl-shared.SpeculationBarrier.0" file="shared_pseudocode.xml" hover="function: SpeculationBarrier()">SpeculationBarrier</a>();</pstext>
    </ps>
  </ps_section>
</instructionsection>
