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<instructionsection id="SUB_ADR" title="SUB (immediate, from PC) -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="SUB" />
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="ADR" />
  </docvars>
  <heading>SUB (immediate, from PC)</heading>
  <desc>
    <brief>Subtract from PC</brief>
    <longer> subtracts an immediate value from the Align(PC, 4) value to form a PC-relative address, and writes the result to the destination register.  Arm recommends that, where possible, software avoids using this alias</longer>
  </desc>
  <aliasto refiform="adr.xml" iformid="ADR">ADR</aliasto>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A2" oneof="2" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_A2" oneofinclass="1" oneof="2" label="A2">
        <docvars>
          <docvar key="alias_mnemonic" value="SUB" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_const" hover="An immediate value">&lt;const&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_A2">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_2" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>imm12 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="2" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" name="i" usename="1">
          <c></c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="o1" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="SUB_ADR_T2" oneofinclass="1" oneof="2" label="T2">
        <docvars>
          <docvar key="alias_mnemonic" value="SUB" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADR" />
        </docvars>
        <asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, PC, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field &quot;i:imm3:imm8&quot;)">&lt;imm12&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="adr.xml#ADR_T2">ADR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, </text><a link="sa_label_1" hover="The label of an instruction or literal data item whose address is to be loaded into {syntax{&lt;Rd&gt;}}">&lt;label&gt;</a></asmtemplate>
          <aliascond>i:imm3:imm8 == '000000000000'</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2, SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A2" />
        </docvars>
        <intro>
          <para>For encoding A2: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T2" />
        </docvars>
        <intro>
          <para>For encoding T2: is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_label_2">&lt;label&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="armarmheading" value="A2" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A2: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding A1 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding A2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are any of the constants described in <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="2">
      <symbol link="sa_label_1">&lt;label&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: the label of an instruction or literal data item whose address is to be loaded into <syntax>&lt;Rd&gt;</syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the <instruction>ADR</instruction> instruction to this label.</para>
          <para>If the offset is zero or positive, encoding T3 is used, with <field>imm32</field> equal to the offset.</para>
          <para>If the offset is negative, encoding T2 is used, with <field>imm32</field> equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of <field>imm32</field>.</para>
          <para>Permitted values of the size of the offset are 0-4095.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_T2" symboldefcount="1">
      <symbol link="sa_imm12">&lt;imm12&gt;</symbol>
      <account encodedin="i:imm3:imm8">
        <intro>
          <para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SUB_ADR_A2" symboldefcount="1">
      <symbol link="sa_const">&lt;const&gt;</symbol>
      <account encodedin="imm12">
        <intro>
          <para>An immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
