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<instructionsection id="CPS" title="CPS, CPSID, CPSIE -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>CPS, CPSID, CPSIE</heading>
  <desc>
    <brief>
      <para>Change PE State</para>
    </brief>
    <authored>
      <para>Change PE State changes one or more of the <xref linkend="BEIDIGBH">PSTATE</xref>.{A, I, F} interrupt mask bits and, optionally, the <xref linkend="BEIDIGBH">PSTATE</xref>.M mode field, without changing any other <xref linkend="BEIDIGBH">PSTATE</xref> bits.</para>
      <para><instruction>CPS</instruction> is treated as <instruction>NOP</instruction> if executed in User mode unless it is defined as being <arm-defined-word>constrained unpredictable</arm-defined-word> elsewhere in this section.</para>
      <para>The PE checks whether the value being written to PSTATE.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Hint instructions: In encoding T2, if the <field>imod</field> field is <binarynumber>00</binarynumber> and the <field>M</field> bit is <binarynumber>0</binarynumber>, a hint instruction is encoded. To determine which hint instruction, see <xref linkend="T32.encoding_index.bcrtrl">Branches and miscellaneous control</xref>.</para>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="3">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="3" id="iclass_a1" no_encodings="5" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="5"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/CPS/A1_AS.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="2" name="imod" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="17" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="16" name="op" settings="1">
          <c>0</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="9" name="E" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="8" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="5" settings="1">
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="CPS_A1_AS" oneofinclass="5" oneof="12" label="Change mode" bitdiffs="imod == 00 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPS" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_A1_AS" oneofinclass="5" oneof="12" label="Interrupt disable" bitdiffs="imod == 11 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_A1_ASM" oneofinclass="5" oneof="12" label="Interrupt disable and change mode" bitdiffs="imod == 11 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-id-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text> , #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_A1_AS" oneofinclass="5" oneof="12" label="Interrupt enable" bitdiffs="imod == 10 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_A1_ASM" oneofinclass="5" oneof="12" label="Interrupt enable and change mode" bitdiffs="imod == 10 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cps-type" value="cps-ie-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="19" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="17" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text> , #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/A1_AS.txt" mylink="aarch32.instrs.CPS.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if mode != '00000' &amp;&amp; M == '0' then UNPREDICTABLE;
if (imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000') || (imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000') then UNPREDICTABLE;
enable = (imod == '10');  disable = (imod == '11');  changemode = (M == '1');
affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');
if (imod == '00' &amp;&amp; M == '0') || imod == '01' then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod == '01'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod == '00' &amp;&amp; M == '0'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">mode != '00000' &amp;&amp; M == '0'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="changemode = TRUE" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the value specified by mode is ignored. There are no additional side-effects.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '0'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F has an <arm-defined-word>unknown</arm-defined-word> nonzero value.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '1'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F == '000'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="3" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/CPS/T1_AS.txt">
        <box hibit="31" width="10" settings="10">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="im" usename="1">
          <c></c>
        </box>
        <box hibit="19" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="18" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="17" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="16" name="F" usename="1">
          <c></c>
        </box>
      </regdiagram>
      <encoding name="CPSID_T1_AS" oneofinclass="2" oneof="12" label="Interrupt disable" bitdiffs="im == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="20" width="1" name="im">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T1_AS" oneofinclass="2" oneof="12" label="Interrupt enable" bitdiffs="im == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="20" width="1" name="im">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/T1_AS.txt" mylink="aarch32.instrs.CPS.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if A:I:F == '000' then UNPREDICTABLE;
enable = (im == '0');  disable = (im == '1');  changemode = FALSE;
affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">A:I:F == '000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T2" oneof="3" id="iclass_t2" no_encodings="5" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="5"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/CPS/T2_AS.txt">
        <box hibit="31" width="12" settings="12">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="13" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="12" settings="1">
          <c>0</c>
        </box>
        <box hibit="11" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="10" width="2" name="imod" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="8" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="A" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="I" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="F" usename="1">
          <c></c>
        </box>
        <box hibit="4" width="5" name="mode" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="CPS_T2_AS" oneofinclass="5" oneof="12" label="Change mode" bitdiffs="imod == 00 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPS" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_T2_AS" oneofinclass="5" oneof="12" label="Interrupt disable" bitdiffs="imod == 11 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-id" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID.W </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSID_T2_ASM" oneofinclass="5" oneof="12" label="Interrupt disable and change mode" bitdiffs="imod == 11 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-id-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSID" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSID</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text>, #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T2_AS" oneofinclass="5" oneof="12" label="Interrupt enable" bitdiffs="imod == 10 &amp;&amp; M == 0">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-ie" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE.W </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CPSIE_T2_ASM" oneofinclass="5" oneof="12" label="Interrupt enable and change mode" bitdiffs="imod == 10 &amp;&amp; M == 1">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="cps-type" value="cps-ie-mode" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="CPSIE" />
        </docvars>
        <box hibit="10" width="2" name="imod">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>CPSIE</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_iflags" hover="Sequence of one or more of following, specifying which interrupt mask bits are affected:&#10;$a: Sets the A bit in the instruction, causing the specified effect on {xref{ARMARM_BEIDIGBH}{PSTATE}}">&lt;iflags&gt;</a><text>, #</text><a link="sa_mode" hover="Number of mode to change to [0-31] (field &quot;mode&quot;)">&lt;mode&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/CPS/T2_AS.txt" mylink="aarch32.instrs.CPS.T2_AS.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if imod == '00' &amp;&amp; M == '0' then SEE "Hint instructions";
if mode != '00000' &amp;&amp; M == '0' then UNPREDICTABLE;
if (imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000') || (imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000') then UNPREDICTABLE;
enable = (imod == '10');  disable = (imod == '11');  changemode = (M == '1');
affectA = (A == '1');  affectI = (I == '1');  affectF = (F == '1');
if imod == '01' || <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod == '01'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">mode != '00000' &amp;&amp; M == '0'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_ADDITIONAL_DECODE">
            <cu_type_variable name="pseudocode" value="changemode = TRUE" />
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as described, and the value specified by mode is ignored. There are no additional side-effects.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod&lt;1&gt; == '1' &amp;&amp; A:I:F == '000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '0'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F has an <arm-defined-word>unknown</arm-defined-word> nonzero value.</cu_type_text>
          </cu_type>
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">imod&lt;1&gt; == '0' &amp;&amp; A:I:F != '000'</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The instruction behaves as if imod&lt;1&gt; == '1'.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction behaves as if A:I:F == '000'.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CPS_A1_AS, CPSIE_T1_AS, CPS_T2_AS" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CPSIE_A1_AS, CPSIE_T1_AS, CPSIE_T2_AS" symboldefcount="1">
      <symbol link="sa_iflags">&lt;iflags&gt;</symbol>
      <account encodedin="A:I:F">
        <intro>
          <para>Is a sequence of one or more of the following, specifying which interrupt mask bits are affected:</para>
          <list type="param">
            <listitem>
              <param>a</param><content>Sets the A bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.A, the SError interrupt mask bit.</content>
            </listitem>
            <listitem>
              <param>i</param><content>Sets the I bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.I, the IRQ interrupt mask bit.</content>
            </listitem>
            <listitem>
              <param>f</param><content>Sets the F bit in the instruction, causing the specified effect on <xref linkend="BEIDIGBH">PSTATE</xref>.F, the FIQ interrupt mask bit.</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CPS_A1_AS, CPS_T2_AS" symboldefcount="1">
      <symbol link="sa_mode">&lt;mode&gt;</symbol>
      <account encodedin="mode">
        <intro>
          <para>Is the number of the mode to change to, in the range 0 to 31, encoded in the "mode" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/CPS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then
    EncodingSpecificOperations();
    if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
        if enable then
            if affectA then PSTATE.A = '0';
            if affectI then PSTATE.I = '0';
            if affectF then PSTATE.F = '0';
        if disable then
            if affectA then PSTATE.A = '1';
            if affectI then PSTATE.I = '1';
            if affectF then PSTATE.F = '1';
        if changemode then
            // AArch32.WriteModeByInstr() sets PSTATE.IL to 1 if this is an illegal mode change.
            <a link="AArch32.WriteModeByInstr.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</a>(mode);
else
    EncodingSpecificOperations();
    if PSTATE.EL != <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
        if enable then
            if affectA then PSTATE.A = '0';
            if affectI then PSTATE.I = '0';
            if affectF then PSTATE.F = '0';
        if disable then
            if affectA then PSTATE.A = '1';
            if affectI then PSTATE.I = '1';
            if affectF then PSTATE.F = '1';
        if changemode then
            // AArch32.WriteModeByInstr() sets PSTATE.IL to 1 if this is an illegal mode change.
            <a link="AArch32.WriteModeByInstr.1" file="shared_pseudocode.xml" hover="function: AArch32.WriteModeByInstr(bits(5) mode)">AArch32.WriteModeByInstr</a>(mode);</pstext>
    </ps>
  </ps_section>
</instructionsection>
