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<instructionsection id="BX" title="BX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BX" />
  </docvars>
  <heading>BX</heading>
  <desc>
    <brief>
      <para>Branch and Exchange</para>
    </brief>
    <authored>
      <para>Branch and Exchange causes a branch to an address and instruction set specified by a register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BX/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="8" settings="8">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="19" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="18" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="10" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="9" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="8" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="7" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="BX_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BX" />
        </docvars>
        <asmtemplate><text>BX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm_1" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BX/A1_A.txt" mylink="aarch32.instrs.BX.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BX" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/BX/T1_A.txt">
        <box hibit="31" width="8" settings="8">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="18" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="17" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="16" settings="1">
          <c>(0)</c>
        </box>
      </regdiagram>
      <encoding name="BX_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BX" />
        </docvars>
        <asmtemplate><text>BX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rm" hover="General-purpose register holding address to be branched to (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BX/T1_A.txt" mylink="aarch32.instrs.BX.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BX_A1, BX_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_A1, BX_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_A1" symboldefcount="1">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BX_T1" symboldefcount="2">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. The PC can be used.</para>
          <note>
            <para>If <syntax>&lt;Rm&gt;</syntax> is the PC at a non word-aligned address, it results in <arm-defined-word>unpredictable</arm-defined-word> behavior because the address passed to the <function>BXWritePC()</function> pseudocode function has bits&lt;1:0&gt; = '10'.</para>
          </note>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BX/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="impl-aarch32.BXWritePC.2" file="shared_pseudocode.xml" hover="function: BXWritePC(bits(32) address_in, BranchType branch_type)">BXWritePC</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</pstext>
    </ps>
  </ps_section>
</instructionsection>
