<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VQSHRN" title="VQSHRN, VQSHRUN -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VQSHRN, VQSHRUN</heading>
  <desc>
    <brief>
      <para>Vector Saturating Shift Right, Narrow</para>
    </brief>
    <authored>
      <para>Vector Saturating Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the truncated results in a doubleword vector.</para>
      <para>For rounded results, see <xref linkend="A32T32-fpsimd.instructions.VQRSHRN">VQRSHRN and VQRSHRUN</xref>.</para>
      <para>The operand elements must all be the same size, and can be any one of:</para>
      <list type="unordered">
        <listitem><content>16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
        <listitem><content>16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
      </list>
      <para>The result elements are half the width of the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.</para>
      <para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VQSHRN/T1A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="23" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_A1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHRUN_A1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VQSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="24" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if imm6 IN {'000xxx'} then SEE "Related encodings";
if U == '0' &amp;&amp; op == '0' then SEE "VSHRN";
if Vm&lt;0&gt; == '1' then UNDEFINED;
integer esize;
integer elements;
integer shift_amount;
case imm6 of
    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VQSHRN/T1A1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="6" name="imm6" usename="1">
          <c colspan="6"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" name="op" usename="1">
          <c></c>
        </box>
        <box hibit="7" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" name="Q" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VQSHRN_T1" oneofinclass="2" oneof="4" label="Signed result" bitdiffs="!(imm6 == 000xxx) &amp;&amp; op == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHRN" />
          <docvar key="result-type" value="signed-result" />
        </docvars>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>1</c>
        </box>
        <asmtemplate><text>VQSHRN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type" hover="Data type for elements of vectors (field &quot;U&quot;) [S,U]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VQSHRUN_T1" oneofinclass="2" oneof="4" label="Unsigned result" bitdiffs="U == 1 &amp;&amp; !(imm6 == 000xxx) &amp;&amp; op == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VQSHRUN" />
          <docvar key="result-type" value="unsigned-result" />
        </docvars>
        <box hibit="28" width="1" name="U">
          <c>1</c>
        </box>
        <box hibit="21" width="15" name="imm6">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c></c>
          <c></c>
          <c></c>
        </box>
        <box hibit="8" width="1" name="op">
          <c>0</c>
        </box>
        <asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_type_1" hover="Data type for elements of vectors (field &quot;U&quot;) [S]">&lt;type&gt;</a><a link="sa_size" hover="Data size for elements of vectors (field &quot;imm6&lt;5:3&gt;&quot;) [16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_imm" hover="Immediate value [1-{syntax{&lt;size&gt;}}/2] (field &quot;imm6&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VQSHRN/T1A1_A.txt" mylink="aarch32.instrs.VQSHRN.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if imm6 IN {'000xxx'} then SEE "Related encodings";
if U == '0' &amp;&amp; op == '0' then SEE "VSHRN";
if Vm&lt;0&gt; == '1' then UNDEFINED;
integer esize;
integer elements;
integer shift_amount;
case imm6 of
    when '001xxx'  esize = 8;  elements = 8;  shift_amount = 16 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
    when '01xxxx'  esize = 16;  elements = 4;  shift_amount = 32 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
    when '1xxxxx'  esize = 32;  elements = 2;  shift_amount = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
src_unsigned = (U == '1' &amp;&amp; op == '1');  dest_unsigned = (U == '1');
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VQSHRN_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_type">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the signed result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">U</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRUN_A1, VQSHRUN_T1" symboldefcount="2">
      <symbol link="sa_type_1">&lt;type&gt;</symbol>
      <definition encodedin="U">
        <intro>For the unsigned result variant: is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">&lt;type&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">S</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="imm6&lt;5:3&gt;">
        <intro>Is the data size for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm6&lt;5:3&gt;</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">001</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">01x</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">1xx</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VQSHRN_A1, VQSHRN_T1" symboldefcount="1">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm6">
        <intro>
          <para>Is an immediate value, in the range 1 to <syntax>&lt;size&gt;</syntax>/2, encoded in the "imm6" field as <syntax>&lt;size&gt;</syntax>/2 - <syntax>&lt;imm&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VQSHRN/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();  <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
    for e = 0 to elements-1
        operand = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[m&gt;&gt;1],e,2*esize], src_unsigned);
        (result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(operand &gt;&gt; shift_amount, esize, dest_unsigned);
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d],e,esize] = result;
        if sat then FPSCR.QC = '1';</pstext>
    </ps>
  </ps_section>
</instructionsection>
