<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="VCMLA" title="VCMLA -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCMLA" />
  </docvars>
  <heading>VCMLA</heading>
  <desc>
    <brief>
      <para>Vector Complex Multiply Accumulate</para>
    </brief>
    <authored>
      <para>Vector Complex Multiply Accumulate.</para>
      <para>This instruction operates on complex numbers that are represented in SIMD&amp;FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers and the destination register:</para>
      <list type="unordered">
        <listitem><content>Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees.</content></listitem>
        <listitem><content>The two elements of the transformed complex number are multiplied by:<list type="unordered"><listitem><content>The real element of the complex number from the first source register, if the transformation was a rotation by 0 or 180 degrees.</content></listitem><listitem><content>The imaginary element of the complex number from the first source register, if the transformation was a rotation by 90 or 270 degrees.</content></listitem></list></content></listitem>
        <listitem><content>The complex number resulting from that multiplication is added to the complex number from the destination register.</content></listitem>
      </list>
      <para>The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCMLA/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA/A1_A.txt" mylink="aarch32.instrs.VCMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;
if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);
if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;
elements = 64 DIV esize;
regs = if Q == '0' then 1 else 2;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCMLA" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.3" feature="FEAT_FCMA" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCMLA/T1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="2" name="rot" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="op3" settings="1">
          <c>0</c>
        </box>
        <box hibit="9" settings="1">
          <c>0</c>
        </box>
        <box hibit="8" name="op4" settings="1">
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCMLA_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VCMLA_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCMLA" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VCMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;S&quot;) [F16,F32]">&lt;dt&gt;</a><text> </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #</text><a link="sa_rotate" hover="Rotation applied to elements in the second SIMD&amp;FP source register (field &quot;rot&quot;) [0,90,180,270]">&lt;rotate&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCMLA/T1_A.txt" mylink="aarch32.instrs.VCMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if !<a link="impl-shared.HaveFCADDExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFCADDExt()">HaveFCADDExt</a>() then UNDEFINED;
if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
esize = 16 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(S);
if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() &amp;&amp; esize == 16 then UNDEFINED;
elements = 64 DIV esize;
regs = if Q == '0' then 1 else 2;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dt">&lt;dt&gt;</symbol>
      <definition encodedin="S">
        <intro>Is the data type for the elements of the vectors, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">S</entry>
                <entry class="symbol">&lt;dt&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">F16</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">F32</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qn">&lt;Qn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_Q, VCMLA_T1_Q" symboldefcount="1">
      <symbol link="sa_qm">&lt;Qm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCMLA_A1_D, VCMLA_T1_D" symboldefcount="1">
      <symbol link="sa_rotate">&lt;rotate&gt;</symbol>
      <definition encodedin="rot">
        <intro>Is the rotation to be applied to elements in the second SIMD&amp;FP source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">rot</entry>
                <entry class="symbol">&lt;rotate&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">0</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">90</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">180</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">270</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations();
<a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
for r = 0 to regs-1
    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r];
    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r];
    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];
    for e = 0 to (elements DIV 2)-1
        bits(esize) element1;
        bits(esize) element2;
        bits(esize) element3;
        bits(esize) element4;
        case rot of
            when '00'
                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize];
                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];
                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize];
                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];
            when '01'
                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize]);
                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];
                element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize];
                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];
            when '10'
                element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize]);
                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];
                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize]);
                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2,esize];
            when '11'
                element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2+1,esize];
                element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];
                element3 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2,e*2,esize]);
                element4 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1,e*2+1,esize];
        result1 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2,esize],element2,element1, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
        result2 = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3,e*2+1,esize],element4,element3, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2,esize] = result1;
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e*2+1,esize] = result2;</pstext>
    </ps>
  </ps_section>
</instructionsection>
