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<instructionsection id="VLD1_m" title="VLD1 (multiple single elements) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VLD1" />
  </docvars>
  <heading>VLD1 (multiple single elements)</heading>
  <desc>
    <brief>
      <para>Load multiple single 1-element structures to one, two, three, or four registers</para>
    </brief>
    <authored>
      <para>Load multiple single 1-element structures to one, two, three, or four registers loads elements from memory into one, two, three, or four registers, without de-interleaving. Every element of each register is loaded. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGBIHAI">VLD1 (multiple single elements)</xref>.</para>
      <para>Related encodings: See <xref linkend="T32.encoding_index.vldst">Advanced SIMD element or structure load/store</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimdls">Advanced SIMD element or structure load/store</xref> for the A32 instruction set.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
    </syntaxnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="8">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>, </txt>
      <a href="#iclass_a2">A2</a>
      <txt>, </txt>
      <a href="#iclass_a3">A3</a>
      <txt> and </txt>
      <a href="#iclass_a4">A4</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="8" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T1A1_A.txt" mylink="aarch32.instrs.VLD1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="A2" oneof="8" id="iclass_a2" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T2A2_A.txt" mylink="aarch32.instrs.VLD1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 2;  if align == '11' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A3" oneof="8" id="iclass_a3" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T3A3_A.txt" mylink="aarch32.instrs.VLD1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="A4" oneof="8" id="iclass_a4" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VLD1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_A4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_A4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="A4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T4A4_A.txt" mylink="aarch32.instrs.VLD1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 4;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="8" id="iclass_t1" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T1_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T1_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T1_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T1A1_A.txt" mylink="aarch32.instrs.VLD1_m.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 1;  if align&lt;1&gt; == '1' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="8" id="iclass_t2" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T2A2_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T2_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T2_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T2_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T2A2_A.txt" mylink="aarch32.instrs.VLD1_m.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 2;  if align == '11' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T2" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T3" oneof="8" id="iclass_t3" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T3A3_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T3_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T3_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T3_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T3A3_A.txt" mylink="aarch32.instrs.VLD1_m.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 3;  if align&lt;1&gt; == '1' then UNDEFINED;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T4" oneof="8" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VLD1" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VLD1_m/T4A4_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="L" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="itype" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="size" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="align" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VLD1_m_T4_nowb" oneofinclass="3" oneof="24" label="Offset" bitdiffs="Rm == 1111">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T4_posti" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm == 1101">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>]!</text></asmtemplate>
      </encoding>
      <encoding name="VLD1_m_T4_postr" oneofinclass="3" oneof="24" label="Post-indexed" bitdiffs="Rm != 11x1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="address-offset" value="reg-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VLD1" />
        </docvars>
        <box hibit="3" width="4" name="Rm">
          <c>N</c>
          <c>N</c>
          <c></c>
          <c>N</c>
        </box>
        <asmtemplate><text>VLD1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field &quot;size&quot;) [8,16,32,64]">&lt;size&gt;</a><text> </text><a link="sa_list" hover="List containing the 64-bit names of SIMD&amp;FP registers (field &quot;D:Vd&quot;)">&lt;list&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>{</text><text>:</text><a link="sa_align" hover="Optional alignment (field &quot;align&quot;)">&lt;align&gt;</a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VLD1_m/T4A4_A.txt" mylink="aarch32.instrs.VLD1_m.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">regs = 4;
alignment = if align == '00' then 1 else 4 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(align);
ebytes = 1 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);  elements = 8 DIV ebytes;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
wback = (m != 15);  register_index = (m != 15 &amp;&amp; m != 13);
if n == 15 || d+regs &gt; 32 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">d+regs &gt; 32</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1, A2, A3 and A4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2, T3 and T4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <definition encodedin="size">
        <intro>Is the data size, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;size&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">16</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">32</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">64</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_list">&lt;list&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is a list containing the 64-bit names of the SIMD&amp;FP registers.</para>
          <para>The list must be one of:</para>
          <list type="param">
            <listitem>
              <param><syntax>{ &lt;Dd&gt; }</syntax></param><content>Single register. Selects the A1 and T1 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt; }</syntax></param><content>Two single-spaced registers. Selects the A2 and T2 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt; }</syntax></param><content>Three single-spaced registers. Selects the A3 and T3 encodings of the instruction.</content>
            </listitem>
            <listitem>
              <param><syntax>{ &lt;Dd&gt;, &lt;Dd+1&gt;, &lt;Dd+2&gt;, &lt;Dd+3&gt; }</syntax></param><content>Four single-spaced registers. Selects the A4 and T4 encodings of the instruction.</content>
            </listitem>
          </list>
          <para>The register <syntax>&lt;Dd&gt;</syntax> is encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_nowb, VLD1_m_A2_nowb, VLD1_m_A3_nowb, VLD1_m_A4_nowb, VLD1_m_T1_nowb, VLD1_m_T2_nowb, VLD1_m_T3_nowb, VLD1_m_T4_nowb" symboldefcount="1">
      <symbol link="sa_align">&lt;align&gt;</symbol>
      <account encodedin="align">
        <intro>
          <para>Is the optional alignment.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and is encoded in the "align" field as <binarynumber>0b00</binarynumber>.</para>
          <para>Whenever <syntax>&lt;align&gt;</syntax> is present, the permitted values are:</para>
          <list type="param">
            <listitem>
              <param>64</param><content>64-bit alignment, encoded in the "align" field as <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>128</param><content>128-bit alignment, encoded in the "align" field as <binarynumber>0b10</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains two or four registers.</content>
            </listitem>
            <listitem>
              <param>256</param><content>256-bit alignment, encoded in the "align" field as <binarynumber>0b11</binarynumber>. Available only if <syntax>&lt;list&gt;</syntax> contains four registers.</content>
            </listitem>
          </list>
          <para><value>:</value> is the preferred separator before the <syntax>&lt;align&gt;</syntax> value, but the alignment can be specified as <value>@&lt;align&gt;</value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VLD1_m_A1_postr, VLD1_m_A2_postr, VLD1_m_A3_postr, VLD1_m_A4_postr, VLD1_m_T1_postr, VLD1_m_T2_postr, VLD1_m_T3_postr, VLD1_m_T4_postr" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VLD1_m/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();

    address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    <a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_LOAD" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a>, nontemporal, tagchecked);
    if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then
        <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));

    for r = 0 to regs-1
        for e = 0 to elements-1
            bits(ebytes*8) data;
            if ebytes != 8 then
                data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,ebytes];
            else
                if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, ebytes) &amp;&amp; <a link="impl-shared.AlignmentEnforced.0" file="shared_pseudocode.xml" hover="function: boolean AlignmentEnforced()">AlignmentEnforced</a>() then
                    <a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));

                if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then
                    data&lt;31:0&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+4,4];
                    data&lt;63:32&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];
                else
                    data&lt;31:0&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,4];
                    data&lt;63:32&gt; = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+4,4];

            <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,8*ebytes] = data;
            address = address + ebytes;
    if wback then
        if register_index then
            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];
        else
            <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 8*regs;</pstext>
    </ps>
  </ps_section>
</instructionsection>
