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<instructionsection id="BFC" title="BFC -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="BFC" />
  </docvars>
  <heading>BFC</heading>
  <desc>
    <brief>
      <para>Bit Field Clear</para>
    </brief>
    <authored>
      <para>Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="BFC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/BFC/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="7" settings="7">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="lsb" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="BFC_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="BFC" />
        </docvars>
        <asmtemplate><text>BFC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_lsb_1" hover="Least significant bit to be cleared [0-31] (field &quot;lsb&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be cleared [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFC/A1_A.txt" mylink="aarch32.instrs.BFC.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(lsb);
if d == 15 then UNPREDICTABLE;
if msbit &lt; lsbit then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">msbit &lt; lsbit</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="BFC" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/BFC/T1_A.txt">
        <box hibit="31" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="26" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="op1&lt;2:1&gt;" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" name="op1&lt;0&gt;" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="4" width="5" name="msb" usename="1">
          <c colspan="5"></c>
        </box>
      </regdiagram>
      <encoding name="BFC_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="BFC" />
        </docvars>
        <asmtemplate><text>BFC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>, #</text><a link="sa_lsb" hover="Least significant bit that is to be cleared [0-31] (field &quot;imm3:imm2&quot;)">&lt;lsb&gt;</a><text>, #</text><a link="sa_width" hover="Number of bits to be cleared [1-32-&lt;lsb&gt;] (field &quot;msb&quot;)">&lt;width&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/BFC/T1_A.txt" mylink="aarch32.instrs.BFC.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  msbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msb);  lsbit = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3:imm2);
if d == 15 then UNPREDICTABLE;  // Armv8-A removes UNPREDICTABLE for R13
if msbit &lt; lsbit then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">msbit &lt; lsbit</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1" symboldefcount="1">
      <symbol link="sa_lsb_1">&lt;lsb&gt;</symbol>
      <account encodedin="lsb">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the least significant bit to be cleared, in the range 0 to 31, encoded in the "lsb" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_T1" symboldefcount="2">
      <symbol link="sa_lsb">&lt;lsb&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the least significant bit that is to be cleared, in the range 0 to 31, encoded in the "imm3:imm2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFC_A1, BFC_T1" symboldefcount="1">
      <symbol link="sa_width">&lt;width&gt;</symbol>
      <account encodedin="msb">
        <intro>
          <para>Is the number of bits to be cleared, in the range 1 to 32-&lt;lsb&gt;, encoded in the "msb" field as &lt;lsb&gt;+&lt;width&gt;-1.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/BFC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]&lt;msbit:lsbit&gt; = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>('0', (msbit-lsbit)+1);
    // Other bits of R[d] are unchanged</pstext>
    </ps>
  </ps_section>
</instructionsection>
