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<instructionsection id="VSEL" title="VSELEQ, VSELGE, VSELGT, VSELVS -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
  </docvars>
  <heading>VSELEQ, VSELGE, VSELGT, VSELVS</heading>
  <desc>
    <brief>
      <para>Floating-point conditional select</para>
    </brief>
    <authored>
      <para>Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the <xref linkend="CJAGBHBH">APSR</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="12" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="12"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/VSEL/A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="cc" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSELEQ_A1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_A1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_A1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_A1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_A1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_A1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Cannot be conditional"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSEL/A1_A.txt" mylink="aarch32.instrs.VSEL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
integer esize;
integer d;
integer n;
integer m;
case size of
    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
cond = cc:(cc&lt;1&gt; EOR cc&lt;0&gt;):'0';</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="12" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="12"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/VSEL/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" name="cc" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
          <c colspan="2">!= 00</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" settings="1">
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VSELEQ_T1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_T1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELEQ_T1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELEQ" />
          <docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGE_T1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGE" />
          <docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELGT_T1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELGT" />
          <docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 01">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="halfprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
        </docvars>
        <arch_variants>
          <arch_variant name="ARMv8.2" feature="FEAT_FP16" />
        </arch_variants>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 10">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="VSELVS_T1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 &amp;&amp; size == 11">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VSELVS" />
          <docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
        </docvars>
        <box hibit="21" width="2" name="cc">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="9" width="2" name="size">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate comment="Not permitted in IT block"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VSEL/T1_A.txt" mylink="aarch32.instrs.VSEL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if size == '00' || (size == '01' &amp;&amp; !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
integer esize;
integer d;
integer n;
integer m;
case size of
    when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
    when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
    when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
cond = cc:(cc&lt;1&gt; EOR cc&lt;0&gt;):'0';</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">InITBlock()</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type>
            <cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
          </cu_type>
          <cu_type>
            <cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
          </cu_type>
          <arch_variants>
            <arch_variant name="ARMv8.2-A" />
          </arch_variants>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="M:Vm">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VSEL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
case esize of
    when 16
        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : (if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m])&lt;15:0&gt;;
    when 32
        <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];
    when 64
        <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n] else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</pstext>
    </ps>
  </ps_section>
</instructionsection>
