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<instructionsection id="VCVTB_bfs" title="VCVTB (BFloat16) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VCVTB" />
  </docvars>
  <heading>VCVTB (BFloat16)</heading>
  <desc>
    <brief>
      <para>Converts from a single-precision value to a BFloat16 value in the bottom half of a single-precision register</para>
    </brief>
    <authored>
      <para>Converts the single-precision value in a single-precision register to BFloat16 format and writes the result into the bottom half of a single precision register, preserving the top 16 bits of the destination register.</para>
      <para>Unlike the BFloat16 multiplication instructions, this instruction honors all the control bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> that apply to single-precision arithmetic, including the rounding mode. This instruction can generate a floating-point exception which causes a cumulative exception bit in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set, or a synchronous exception to be taken, depending on the enable bits in the <xref linkend="AArch32.fpscr">FPSCR</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_A1_bfs" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" mylink="aarch32.instrs.VCVTB_bf16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VCVTB" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VCVTB_bf16/T1A1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="19" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="18" width="3" name="opc2" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="7" name="o3" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" settings="1">
          <c>1</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VCVTB_T1_bfs" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VCVTB" />
        </docvars>
        <asmtemplate><text>VCVTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16.F32 </text><a link="sa_sd" hover="32-bit SIMD&amp;FP destination register (field &quot;Vd:D&quot;)">&lt;Sd&gt;</a><text>, </text><a link="sa_sm" hover="32-bit SIMD&amp;FP source register (field &quot;Vm:M&quot;)">&lt;Sm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VCVTB_bf16/T1A1_A.txt" mylink="aarch32.instrs.VCVTB_bf16.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_sd">&lt;Sd&gt;</symbol>
      <account encodedin="Vd:D">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Vd:D" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VCVTB_A1_bfs, VCVTB_T1_bfs" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm:M">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Vm:M" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VCVTB_bf16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);

    <a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d]&lt;15:0&gt; = <a link="impl-shared.FPConvertBF.2" file="shared_pseudocode.xml" hover="function: bits(16) FPConvertBF(bits(32) op, FPCRType fpcr)">FPConvertBF</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);</pstext>
    </ps>
  </ps_section>
</instructionsection>
