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<instructionsection id="IT" title="IT -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="T1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="T32" />
    <docvar key="mnemonic" value="IT" />
  </docvars>
  <heading>IT</heading>
  <desc>
    <brief>
      <para>If-Then</para>
    </brief>
    <authored>
      <para>If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the IT block are the same as, or the inverse of, the condition the <instruction>IT</instruction> instruction specifies for the first instruction in the block.</para>
      <para>The <instruction>IT</instruction> instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can change the condition flags.</para>
      <para>16-bit instructions in the IT block, other than <instruction>CMP</instruction>, <instruction>CMN</instruction> and <instruction>TST</instruction>, do not set the condition flags. An <instruction>IT</instruction> instruction with the <value>AL</value> condition can change the behavior without conditional execution.</para>
      <para>The architecture permits exception return to an instruction in the IT block only if the restoration of the <xref linkend="CIHJBHJA">CPSR</xref> restores <xref linkend="BEIDIGBH">PSTATE</xref>.IT to a state consistent with the conditions specified by the <instruction>IT</instruction> instruction.  Any other exception return to an instruction in an IT block is <arm-defined-word>unpredictable</arm-defined-word>. Any branch to a target instruction in an IT block is not permitted, and if such a branch is made it is <arm-defined-word>unpredictable</arm-defined-word> what condition is used when executing that target instruction and any subsequent instruction in the IT block.</para>
      <para>Many uses of the IT instruction are deprecated for performance reasons, and an implementation might include ITD controls that can disable those uses of IT, making them <arm-defined-word>undefined</arm-defined-word>.</para>
      <para>For more information see <xref linkend="BABGABFG">Conditional execution</xref> and <xref linkend="BABHIJHI">Conditional instructions</xref>. The first of these sections includes more information about the ITD controls.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
      <para>Related encodings: <xref linkend="T32.encoding_index.misc16">Miscellaneous 16-bit instructions</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The conditions specified in an <instruction>IT</instruction> instruction must match those specified in the syntax of the instructions in its IT block. When assembling to A32 code, assemblers check <instruction>IT</instruction> instruction syntax for validity but do not generate assembled instructions for them. See <xref linkend="BABHIJHI">Conditional instructions</xref>.</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="T1" oneof="1" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="IT" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/IT/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="23" width="4" name="firstcond" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="19" width="4" name="mask" usename="1" settings="4" constraint="!= 0000">
          <c colspan="4">!= 0000</c>
        </box>
      </regdiagram>
      <encoding name="IT_T1" oneofinclass="1" oneof="1" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="IT" />
        </docvars>
        <asmtemplate><text>IT</text><text>{</text><a link="sa_x" hover="The condition for second instruction in the IT block (field &quot;mask[3]&quot;)">&lt;x&gt;</a><text>{</text><a link="sa_y" hover="The condition for third instruction in the IT block (field &quot;mask[2]&quot;)">&lt;y&gt;</a><text>{</text><a link="sa_z" hover="The condition for fourth instruction in the IT block (field &quot;mask[1]&quot;)">&lt;z&gt;</a><text>}</text><text>}</text><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_cond" hover="The condition for first instruction in the IT block (field &quot;firstcond&quot;)">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/IT/T1_A.txt" mylink="aarch32.instrs.IT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if mask == '0000' then SEE "Related encodings";
if firstcond == '1111' || (firstcond == '1110' &amp;&amp; <a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(mask) != 1) then UNPREDICTABLE;
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">firstcond == '1111' || (firstcond == '1110' &amp;&amp; BitCount(mask) != 1)</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The '1111' condition is treated as being the same as the '1110' condition, meaning always, and the ITSTATE state machine is progressed in the same way as for any other cond_base value.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_x">&lt;x&gt;</symbol>
      <account encodedin="mask[3]">
        <intro>
          <para>The condition for the second instruction in the IT block. If omitted, the "mask" field is set to <binarynumber>0b1000</binarynumber>. If present it is encoded in the "mask[3]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_y">&lt;y&gt;</symbol>
      <account encodedin="mask[2]">
        <intro>
          <para>The condition for the third instruction in the IT block. If omitted and <syntax>&lt;x&gt;</syntax> is present, the "mask[2:0]" field is set to <binarynumber>0b100</binarynumber>. If <syntax>&lt;y&gt;</syntax> is present it is encoded in the "mask[2]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_z">&lt;z&gt;</symbol>
      <account encodedin="mask[1]">
        <intro>
          <para>The condition for the fourth instruction in the IT block. If omitted and <syntax>&lt;y&gt;</syntax> is present, the "mask[1:0]" field is set to <binarynumber>0b10</binarynumber>. If <syntax>&lt;z&gt;</syntax> is present, the "mask[0]" field is set to 1, and it is encoded in the "mask[1]" field:</para>
          <list type="param">
            <listitem>
              <param>T</param><content>firstcond[0]</content>
            </listitem>
            <listitem>
              <param>E</param><content>NOT firstcond[0]</content>
            </listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="IT_T1" symboldefcount="1">
      <symbol link="sa_cond">&lt;cond&gt;</symbol>
      <account encodedin="firstcond">
        <intro>
          <para>The condition for the first instruction in the IT block, encoded in the "firstcond" field. See <xref linkend="Chdcgdjb">Condition codes</xref> for the range of conditions available, and the encodings.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/IT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations();
<a link="AArch32.CheckITEnabled.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckITEnabled(bits(4) mask)">AArch32.CheckITEnabled</a>(mask);
PSTATE.IT&lt;7:0&gt; = firstcond:mask;
ShouldAdvanceIT = FALSE;</pstext>
    </ps>
  </ps_section>
</instructionsection>
