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<instructionsection id="RSC_r" title="RSC, RSCS (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSC, RSCS (register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract with Carry (register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The RSC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSC_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSC_r_A1_RRX" oneofinclass="4" oneof="4" label="RSC, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
          <docvar key="mnemonic-shift-type" value="RSC-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSC_r_A1" oneofinclass="4" oneof="4" label="RSC, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSC" />
          <docvar key="mnemonic-shift-type" value="RSC-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="RSCS_r_A1_RRX" oneofinclass="4" oneof="4" label="RSCS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
          <docvar key="mnemonic-shift-type" value="RSCS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="RSCS_r_A1" oneofinclass="4" oneof="4" label="RSCS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSCS" />
          <docvar key="mnemonic-shift-type" value="RSCS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSC_r/A1_A.txt" mylink="aarch32.instrs.RSC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');
(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax>&lt;Rn&gt;</syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the RSCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSC_r_A1" symboldefcount="1">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <intro>
          <para>Is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, PSTATE.C);
    if d == 15 then
        if setflags then
            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
        else
            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
    else
        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
        if setflags then
            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</pstext>
    </ps>
  </ps_section>
</instructionsection>
