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<instructionsection id="VFMSL_s" title="VFMSL (by scalar) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="mnemonic" value="VFMSL" />
  </docvars>
  <heading>VFMSL (by scalar)</heading>
  <desc>
    <brief>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (by scalar)</para>
    </brief>
    <authored>
      <para>Vector Floating-point Multiply-Subtract Long from accumulator (by scalar). This instruction multiplies the negated vector elements in the first source SIMD&amp;FP register by the specified value in the second source SIMD&amp;FP register, and accumulates the product to the corresponding vector element of the destination SIMD&amp;FP register. The instruction does not round the result of the multiply before the accumulation.</para>
      <para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
      <para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
      <note>
        <para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="32" psname="aarch32/instrs/VFMAL_i/A1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMSL_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/A1_A.txt" mylink="aarch32.instrs.VFMAL_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;

integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);

integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);
integer esize = 32;
integer regs = if Q=='1' then 2 else 1;
integer datasize = if Q=='1' then 64 else 32;
boolean sub_op = S=='1';</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="VFMSL" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <arch_variants>
        <arch_variant name="ARMv8.2" feature="FEAT_FHM" />
      </arch_variants>
      <regdiagram form="16x2" psname="aarch32/instrs/VFMAL_i/T1_A.txt" tworows="1">
        <box hibit="31" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="23" name="op1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Vn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" name="N" usename="1">
          <c></c>
        </box>
        <box hibit="6" name="Q" usename="1">
          <c></c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" name="U" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Vm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="VFMSL_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>0</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&amp;FP source register (field &quot;Vn:N&quot;)">&lt;Sn&gt;</a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;:M&quot;)">&lt;Sm&gt;</a><text>[</text><a link="sa_index_1" hover="Element index [0-1] (field &quot;Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="VFMSL_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="VFMSL" />
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <box hibit="6" width="1" name="Q">
          <c>1</c>
        </box>
        <asmtemplate><text>VFMSL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;Vm&lt;2:0&gt;&quot;)">&lt;Dm&gt;</a><text>[</text><a link="sa_index" hover="Element index [0-3] (field &quot;M:Vm&lt;3&gt;&quot;)">&lt;index&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/VFMAL_i/T1_A.txt" mylink="aarch32.instrs.VFMAL_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
if Q == '1' &amp;&amp; Vd&lt;0&gt; == '1' then UNDEFINED;

integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;2:0&gt;:M);

integer index = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm&lt;3&gt;) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm&lt;3&gt;);
integer esize = 32;
integer regs = if Q=='1' then 2 else 1;
integer datasize = if Q=='1' then 64 else 32;
boolean sub_op = S=='1';</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_qd">&lt;Qd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dn">&lt;Dn&gt;</symbol>
      <account encodedin="N:Vn">
        <intro>
          <para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="1">
      <symbol link="sa_dm">&lt;Dm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;">
        <intro>
          <para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_dd">&lt;Dd&gt;</symbol>
      <account encodedin="D:Vd">
        <intro>
          <para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sn">&lt;Sn&gt;</symbol>
      <account encodedin="Vn:N">
        <intro>
          <para>Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Vn:N" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_sm">&lt;Sm&gt;</symbol>
      <account encodedin="Vm&lt;2:0&gt;:M">
        <intro>
          <para>Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Vm&lt;2:0&gt;:M" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_D, VFMSL_s_T1_D" symboldefcount="1">
      <symbol link="sa_index_1">&lt;index&gt;</symbol>
      <account encodedin="Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="double" />
        </docvars>
        <intro>
          <para>For the 64-bit SIMD vector variant: is the element index in the range 0 to 1, encoded in the "Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VFMSL_s_A1_Q, VFMSL_s_T1_Q" symboldefcount="2">
      <symbol link="sa_index">&lt;index&gt;</symbol>
      <account encodedin="M:Vm&lt;3&gt;">
        <docvars>
          <docvar key="simdvectorsize" value="quad" />
        </docvars>
        <intro>
          <para>For the 128-bit SIMD vector variant: is the element index in the range 0 to 3, encoded in the "M:Vm&lt;3&gt;" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/VFMAL_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
bits(datasize) operand1 ;
bits(datasize) operand2 ;
bits(64) operand3;
bits(64) result;
bits(esize DIV 2) element1;
bits(esize DIV 2) element2;

if Q=='0' then
    operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]&lt;datasize-1:0&gt;;
    operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]&lt;datasize-1:0&gt;;
else
    operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]&lt;datasize-1:0&gt;;
    operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]&lt;datasize-1:0&gt;;
element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, index, esize DIV 2];
for r = 0 to regs-1
    operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];
    for e = 0 to 1
        element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];
        if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
        <a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,
                                           <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
    <a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</pstext>
    </ps>
  </ps_section>
</instructionsection>
