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<instructionsection id="RSB_rr" title="RSB, RSBS (register-shifted register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="armarmheading" value="A1" />
    <docvar key="instr-class" value="general" />
    <docvar key="isa" value="A32" />
  </docvars>
  <heading>RSB, RSBS (register-shifted register)</heading>
  <desc>
    <brief>
      <para>Reverse Subtract (register-shifted register)</para>
    </brief>
    <authored>
      <para>Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <iclass name="A1" oneof="1" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/RSB_rr/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rs" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" settings="1">
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="RSBS_rr_A1" oneofinclass="2" oneof="2" label="Flag setting" bitdiffs="S == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSBS" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <asmtemplate><text>RSBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RSB_rr_A1" oneofinclass="2" oneof="2" label="Not flag setting" bitdiffs="S == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="cond-setting" value="no-s" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="RSB" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <asmtemplate><text>RSB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> </text><a link="sa_rs" hover="Third general-purpose source register holding a shift amount in its bottom 8 bits (field &quot;Rs&quot;)">&lt;Rs&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/RSB_rr/A1_A.txt" mylink="aarch32.instrs.RSB_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
setflags = (S == '1');  shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);
if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="RSB_rr_A1" symboldefcount="1">
      <symbol link="sa_rs">&lt;Rs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the third general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/RSB_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]&lt;7:0&gt;);
    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, '1');
    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
    if setflags then
        PSTATE.&lt;N,Z,C,V&gt; = nzcv;</pstext>
    </ps>
  </ps_section>
</instructionsection>
