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<instructionsection id="MCRR" title="MCRR -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="MCRR" />
  </docvars>
  <heading>MCRR</heading>
  <desc>
    <brief>
      <para>Move to System register from two general-purpose registers</para>
    </brief>
    <authored>
      <para>Move to System register from two general-purpose registers. This instruction copies the values of two general-purpose registers to a System register.</para>
      <para>The System register descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
      <para>In an implementation that includes EL2, <instruction>MCRR</instruction> accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MCRR</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception.  For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
      <para>Because of the range of possible traps to Hyp mode, the <instruction>MCRR</instruction> pseudocode does not show these possible traps.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
    <syntaxnotes>
      <para>The possible values of { <syntax>&lt;coproc&gt;</syntax>, <syntax>&lt;opc1&gt;</syntax>, <syntax>&lt;CRm&gt;</syntax> } encode the entire System register encoding space. Not all of this space is allocated, and the System register descriptions identify the allocated encodings.</para>
      <para>For the permitted uses of these instructions, as described in this manual, <syntax>&lt;Rt2&gt;</syntax> transfers bits[63:32] of the selected System register, while <syntax>&lt;Rt&gt;</syntax> transfers bits[31:0].</para>
    </syntaxnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="MCRR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/MCRR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCRR_A1" oneofinclass="1" oneof="2" label="A1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="MCRR" />
        </docvars>
        <asmtemplate><text>MCRR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCRR/T1A1_A.txt" mylink="aarch32.instrs.MCRR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;
if t == 15 || t2 == 15 then UNPREDICTABLE;
// Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="MCRR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/MCRR/T1A1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rt2" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="3" name="coproc&lt;3:1&gt;" usename="1" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="8" name="coproc&lt;0&gt;" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="4" name="opc1" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="3" width="4" name="CRm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="MCRR_T1" oneofinclass="1" oneof="2" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="MCRR" />
        </docvars>
        <asmtemplate><text>MCRR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field &quot;coproc&lt;0&gt;&quot;) [p14,p15]">&lt;coproc&gt;</a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space [0-15] (field &quot;opc1&quot;)">&lt;opc1&gt;</a><text>, </text><a link="sa_rt" hover="First general-purpose register that is transferred into (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, </text><a link="sa_rt2" hover="Second general-purpose register that is transferred into (field &quot;Rt2&quot;)">&lt;Rt2&gt;</a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field &quot;CRm&quot;)">&lt;CRm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/MCRR/T1A1_A.txt" mylink="aarch32.instrs.MCRR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);  cp = if coproc&lt;0&gt; == '0' then 14 else 15;
if t == 15 || t2 == 15 then UNPREDICTABLE;
// Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_coproc">&lt;coproc&gt;</symbol>
      <definition encodedin="coproc&lt;0&gt;">
        <intro>Is the System register encoding space, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">coproc&lt;0&gt;</entry>
                <entry class="symbol">&lt;coproc&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">p14</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">p15</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_opc1">&lt;opc1&gt;</symbol>
      <account encodedin="opc1">
        <intro>
          <para>Is the opc1 parameter within the System register encoding space, in the range 0 to 15, encoded in the "opc1" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the first general-purpose register that is transferred into, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_rt2">&lt;Rt2&gt;</symbol>
      <account encodedin="Rt2">
        <intro>
          <para>Is the second general-purpose register that is transferred into, encoded in the "Rt2" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="MCRR_A1, MCRR_T1" symboldefcount="1">
      <symbol link="sa_crm">&lt;CRm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/MCRR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    <a link="AArch32.SysRegWrite64.4" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWrite64(integer cp_num, bits(32) instr, integer t, integer t2)">AArch32.SysRegWrite64</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t, t2);</pstext>
    </ps>
  </ps_section>
</instructionsection>
