<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->

<instructionsection id="STR_i" title="STR (immediate) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="STR" />
  </docvars>
  <heading>STR (immediate)</heading>
  <desc>
    <brief>
      <para>Store Register (immediate)</para>
    </brief>
    <authored>
      <para>Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="PUSH_STR_i" aliasfile="push_str_i.xml" hover="Push Single Register to Stack" punct=".">
      <text>PUSH (single register)</text>
      <aliaspref labels="A1 (pre-indexed)">P == '1' &amp;&amp; U == '0' &amp;&amp; W == '1' &amp;&amp; Rn == '1101' &amp;&amp; imm12 == '000000000100'</aliaspref>
      <aliaspref labels="T4 (pre-indexed)">Rn == '1101' &amp;&amp; P == '1' &amp;&amp; U == '0' &amp;&amp; W == '1' &amp;&amp; imm8 == '00000100'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink />
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="5">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt>, </txt>
      <a href="#iclass_t3">T3</a>
      <txt> and </txt>
      <a href="#iclass_t4">T4</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="5" id="iclass_a1" no_encodings="3" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/STR_i/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>0</c>
        </box>
        <box hibit="21" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="20" name="o1" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_A1_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STR_i_A1_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STR_i_A1_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="24" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="21" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt_1" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_4" hover="12-bit unsigned immediate byte offset [0-4095] (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/A1_A.txt" mylink="aarch32.instrs.STR_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' &amp;&amp; W == '1' then SEE "STRT";
t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);
index = (P == '1');  add = (U == '1');  wback = (P == '0') || (W == '1');
if wback &amp;&amp; (n == 15 || n == t) then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">wback &amp;&amp; n == t</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">wback &amp;&amp; n == 15</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_WBSUPPRESS" />
          <cu_type>
            <cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STR_i/T1_A.txt">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" name="B" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="21" width="3" name="Rn" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="18" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T1" oneofinclass="1" oneof="9" label="T1">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional positive unsigned immediate byte offset (field &quot;imm5&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T1_A.txt" mylink="aarch32.instrs.STR_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5:'00', 32);
index = TRUE;  add = TRUE;  wback = FALSE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/STR_i/T2_A.txt">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="26" width="3" name="Rt" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="23" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T2" oneofinclass="1" oneof="9" label="T2">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [SP</text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional positive unsigned immediate byte offset (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T2_A.txt" mylink="aarch32.instrs.STR_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = 13;  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);
index = TRUE;  add = TRUE;  wback = FALSE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="base-plus-offset" />
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STR_i/T3_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="12" name="imm12" usename="1">
          <c colspan="12"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T3" oneofinclass="1" oneof="9" label="T3">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <asmtemplate comment="&lt;Rt&gt;, &lt;Rn&gt;, &lt;imm&gt; can be represented in T1 or T2"><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field &quot;imm12&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T3_A.txt" mylink="aarch32.instrs.STR_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then UNDEFINED;
t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);
index = TRUE;  add = TRUE;  wback = FALSE;
if t == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T3" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">t == 15</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T4" oneof="5" id="iclass_t4" no_encodings="3" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T4" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="STR" />
      </docvars>
      <iclassintro count="3"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/STR_i/T4_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" settings="1">
          <c>1</c>
        </box>
        <box hibit="10" name="P" usename="1">
          <c></c>
        </box>
        <box hibit="9" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="8" name="W" usename="1">
          <c></c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="STR_i_T4_off" oneofinclass="3" oneof="9" label="Offset" bitdiffs="P == 1 &amp;&amp; U == 0 &amp;&amp; W == 0">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="9" width="1" name="U">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>0</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <encoding name="STR_i_T4_post" oneofinclass="3" oneof="9" label="Post-indexed" bitdiffs="P == 0 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="post-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>0</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="STR_i_T4_pre" oneofinclass="3" oneof="9" label="Pre-indexed" bitdiffs="P == 1 &amp;&amp; W == 1">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="STR" />
        </docvars>
        <box hibit="10" width="1" name="P">
          <c>1</c>
        </box>
        <box hibit="8" width="1" name="W">
          <c>1</c>
        </box>
        <asmtemplate><text>STR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field &quot;Rt&quot;)">&lt;Rt&gt;</a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_imm_3" hover="8-bit unsigned immediate byte offset [0-255] (field &quot;imm8&quot;)">&lt;imm&gt;</a><text>]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/STR_i/T4_A.txt" mylink="aarch32.instrs.STR_i.T4_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '1' &amp;&amp; U == '1' &amp;&amp; W == '0' then SEE "STRT";
if Rn == '1111' || (P == '0' &amp;&amp; W == '0') then UNDEFINED;
t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);
index = (P == '1');  add = (U == '1');  wback = (W == '1');
if t == 15 || (wback &amp;&amp; n == t) then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T4" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">wback &amp;&amp; n == t</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_STUNKNOWN" />
        </cu_case>
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">t == 15</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type>
            <cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
          </cu_type>
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STR_i_A1_off, STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off, STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_rt_1">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T2, STR_i_T3, STR_i_T4_pre" symboldefcount="2">
      <symbol link="sa_rt">&lt;Rt&gt;</symbol>
      <account encodedin="Rt">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T2, T3 and T4: is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_rn_1">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T3, STR_i_T4_pre" symboldefcount="2">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <docvars>
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1, T3 and T4: is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off, STR_i_T4_pre" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="STR_i_T1, STR_i_T2, STR_i_T3" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the offset is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_A1_off" symboldefcount="1">
      <symbol link="sa_imm_4">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="address-offset" value="signed-offset" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T1" symboldefcount="2">
      <symbol link="sa_imm">&lt;imm&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 124, defaulting to 0 and encoded in the "imm5" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T2" symboldefcount="3">
      <symbol link="sa_imm_1">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T2: is the optional positive unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0 and encoded in the "imm8" field as &lt;imm&gt;/4.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T3" symboldefcount="4">
      <symbol link="sa_imm_2">&lt;imm&gt;</symbol>
      <account encodedin="imm12">
        <docvars>
          <docvar key="address-form" value="base-plus-offset" />
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STR_i_T4_pre" symboldefcount="5">
      <symbol link="sa_imm_3">&lt;imm&gt;</symbol>
      <account encodedin="imm8">
        <docvars>
          <docvar key="address-form" value="pre-indexed" />
          <docvar key="armarmheading" value="T4" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T4: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/STR_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then
    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
        EncodingSpecificOperations();
        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = if t == 15 then <a link="impl-aarch32.PCStoreValue.0" file="shared_pseudocode.xml" hover="function: bits(32) PCStoreValue()">PCStoreValue</a>() else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];
        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;
else
    if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
        EncodingSpecificOperations();
        offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
        address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
        <a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];
        if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</pstext>
    </ps>
  </ps_section>
</instructionsection>
