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<instructionsection id="VPUSH_VSTM" title="VPUSH -- AArch32" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="VPUSH" />
    <docvar key="instr-class" value="fpsimd" />
    <docvar key="ldmstm-mode" value="dec-before" />
    <docvar key="mnemonic" value="VSTMDB" />
  </docvars>
  <heading>VPUSH</heading>
  <desc>
    <brief>
      <para>Push SIMD&amp;FP registers to stack</para>
    </brief>
    <authored>
      <para>Push SIMD&amp;FP registers to stack stores multiple consecutive registers from the Advanced SIMD and floating-point register file to the stack.</para>
    </authored>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
  </operationalnotes>
  <aliasto refiform="vstm.xml" iformid="VSTM">VSTM, VSTMDB, VSTMIA</aliasto>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt> and </txt>
      <a href="#iclass_a2">A2</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt> and </txt>
      <a href="#iclass_t2">T2</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_A1" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="A1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_A1">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="32" psname="" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_A2" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="A2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="A32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_A2">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="fpdatasize" value="doubleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="7" name="imm8&lt;7:1&gt;" usename="1">
          <c colspan="7"></c>
        </box>
        <box hibit="0" name="imm8&lt;0&gt;" usename="1" settings="1">
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_T1" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="fpdatasize" value="doubleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-doubleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_T1">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred (field &quot;D:Vd&quot;)">&lt;dreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="fpdatasize" value="singleprec" />
        <docvar key="instr-class" value="fpsimd" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="" tworows="1">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" name="P" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="U" usename="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" name="D" usename="1">
          <c></c>
        </box>
        <box hibit="21" name="W" usename="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" name="L" settings="1">
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Vd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="2" name="size" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="8" name="imm8" usename="1">
          <c colspan="8"></c>
        </box>
      </regdiagram>
      <encoding name="VPUSH_VSTMDB_T2" oneofinclass="1" oneof="4" label="Decrement Before">
        <docvars>
          <docvar key="alias_mnemonic" value="VPUSH" />
          <docvar key="armarmheading" value="T2" />
          <docvar key="fpdatasize" value="singleprec" />
          <docvar key="instr-class" value="fpsimd" />
          <docvar key="isa" value="T32" />
          <docvar key="ldmstm-mode" value="dec-before" />
          <docvar key="mnemonic" value="VSTMDB" />
          <docvar key="mnemonic-fpdatasize" value="VSTMDB-singleprec" />
        </docvars>
        <asmtemplate><text>VPUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="vstm.xml#VSTMDB_T2">VSTMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier">&lt;size&gt;</a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred (field &quot;Vd:D&quot;)">&lt;sreglist&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T1, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_size">&lt;size&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A2, VPUSH_VSTMDB_T2" symboldefcount="1">
      <symbol link="sa_sreglist">&lt;sreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 32-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="VPUSH_VSTMDB_A1, VPUSH_VSTMDB_T1" symboldefcount="1">
      <symbol link="sa_dreglist">&lt;dreglist&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>Is the list of consecutively numbered 64-bit SIMD&amp;FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
</instructionsection>
