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<instructionsection id="ADD_SP_r" title="ADD, ADDS (SP plus register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>ADD, ADDS (SP plus register)</heading>
  <desc>
    <brief>
      <para>Add to SP (register)</para>
    </brief>
    <authored>
      <para>Add to SP (register) adds an optionally-shifted register value to the SP value, and writes the result to the destination register.</para>
      <para>If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.</para>
      <para>The field descriptions for <syntax>&lt;Rd&gt;</syntax> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:</para>
      <list type="unordered">
        <listitem><content>The ADD variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
        <listitem><content>The ADDS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem><listitem><content>The PE checks SPSR_&lt;current_mode&gt; for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
      </list>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="4">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>, </txt>
      <a href="#iclass_t2">T2</a>
      <txt> and </txt>
      <a href="#iclass_t3">T3</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="4" id="iclass_a1" no_encodings="4" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/ADD_SP_r/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_A1_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_SP_r_A1" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_A1_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_A1" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/A1_A.txt" mylink="aarch32.instrs.ADD_SP_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');
(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_r/T1_A.txt">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="DM" usename="1">
          <c></c>
        </box>
        <box hibit="22" width="4" name="Rs" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="Rdm" usename="1">
          <c colspan="3"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T1" oneofinclass="1" oneof="10" label="T1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rdm" hover="General-purpose destination and second source register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rdm" hover="General-purpose destination and second source register (field &quot;Rdm&quot;)">&lt;Rdm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T1_A.txt" mylink="aarch32.instrs.ADD_SP_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DM:Rdm);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(DM:Rdm);  setflags = FALSE;
(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);
if d == 15 &amp;&amp; <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() &amp;&amp; !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T2" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="ADD" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16" psname="aarch32/instrs/ADD_SP_r/T2_A.txt" tworows="1">
        <box hibit="31" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" name="op" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" name="D" settings="1">
          <c>1</c>
        </box>
        <box hibit="22" width="4" name="Rm" usename="1" settings="4" constraint="!= 1101">
          <c colspan="4">!= 1101</c>
        </box>
        <box hibit="18" width="3" name="Rd" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T2" oneofinclass="1" oneof="10" label="T2">
        <docvars>
          <docvar key="armarmheading" value="T2" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
        </docvars>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_sp" hover="Stack pointer">{SP,}</a><text> SP, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T2_A.txt" mylink="aarch32.instrs.ADD_SP_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rm == '1101' then SEE "encoding T1";
d = 13;  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = FALSE;
(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T3" oneof="4" id="iclass_t3" no_encodings="4" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T3" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="4"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/ADD_SP_r/T3_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="op1" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" name="S" usename="1">
          <c></c>
        </box>
        <box hibit="19" width="4" name="Rn" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="15" settings="1">
          <c>(0)</c>
        </box>
        <box hibit="14" width="3" name="imm3" usename="1">
          <c colspan="3"></c>
        </box>
        <box hibit="11" width="4" name="Rd" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="5" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="ADD_SP_r_T3_RRX" oneofinclass="4" oneof="10" label="ADD, rotate right with extend" bitdiffs="S == 0 &amp;&amp; imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADD_SP_r_T3" oneofinclass="4" oneof="10" label="ADD, shift or rotate by value" bitdiffs="S == 0 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADD" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>0</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate comment="&lt;Rd&gt;, &lt;Rm&gt; can be represented in T1 or T2"><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
        <asmtemplate><text>ADD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_T3_RRX" oneofinclass="4" oneof="10" label="ADDS, rotate right with extend" bitdiffs="S == 1 &amp;&amp; imm3 == 000 &amp;&amp; Rd != 1111 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="imm3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="7" width="2" name="imm2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text>, RRX</text></asmtemplate>
      </encoding>
      <encoding name="ADDS_SP_r_T3" oneofinclass="4" oneof="10" label="ADDS, shift or rotate by value" bitdiffs="S == 1 &amp;&amp; !(imm3 == 000 &amp;&amp; imm2 == 00 &amp;&amp; stype == 11) &amp;&amp; Rd != 1111">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="ADDS" />
          <docvar key="mnemonic-shift-type" value="ADDS-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="20" width="1" name="S">
          <c>1</c>
        </box>
        <box hibit="14" width="11" name="imm3:imm2:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <box hibit="11" width="4" name="Rd">
          <c>N</c>
          <c>N</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>ADDS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field &quot;Rd&quot;)">&lt;Rd&gt;</a><text>,</text><text>}</text><text> SP, </text><a link="sa_rm_1" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR)] (field &quot;imm3:imm2&quot;)">&lt;amount&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/ADD_SP_r/T3_A.txt" mylink="aarch32.instrs.ADD_SP_r.T3_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rd == '1111' &amp;&amp; S == '1' then SEE "CMN (register)";
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  setflags = (S == '1');
(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm3:imm2);
if (d == 15 &amp;&amp; !setflags) || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T1, ADD_SP_r_T2, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T1, ADD_SP_r_T2, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T2" symboldefcount="1">
      <symbol link="sa_sp">SP,</symbol>
      <account encodedin="">
        <intro>
          <para>Is the stack pointer.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T1" symboldefcount="1">
      <symbol link="sa_rdm">&lt;Rdm&gt;</symbol>
      <account encodedin="Rdm">
        <intro>
          <para>Is the general-purpose destination and second source register, encoded in the "Rdm" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch to the address calculated by the operation. This is a simple branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1" symboldefcount="1">
      <symbol link="sa_rd_1">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
          <list type="unordered">
            <listitem><content>For the ADD variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
            <listitem><content>For the ADDS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_&lt;current_mode&gt;.</content></listitem>
          </list>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_rd">&lt;Rd&gt;</symbol>
      <account encodedin="Rd">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T2" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>For encoding A1 and T2: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_rm_1">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic-shift-type" value="ADD-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding T3: is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_A1, ADD_SP_r_T3" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the second source register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="ADD_SP_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="ADD_SP_r_T3" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm3:imm2">
        <docvars>
          <docvar key="armarmheading" value="T3" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T3: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR), encoded in the "imm3:imm2" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/ADD_SP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], shifted, '0');
    if d == 15 then
        if setflags then
            <a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
        else
            <a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
    else
        <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
        if setflags then
            PSTATE.&lt;N,Z,C,V&gt; = nzcv;</pstext>
    </ps>
  </ps_section>
</instructionsection>
