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<instructionsection id="PLI_r" title="PLI (register) -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
    <docvar key="mnemonic" value="PLI" />
  </docvars>
  <heading>PLI (register)</heading>
  <desc>
    <brief>
      <para>Preload Instruction (register)</para>
    </brief>
    <authored>
      <para>Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache.</para>
      <para>The effect of a <instruction>PLI</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/PLI_r/A1_A.txt">
        <box hibit="31" width="7" settings="7">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" name="D" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="U" usename="1">
          <c></c>
        </box>
        <box hibit="22" name="o2" settings="1">
          <c>1</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="14" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="13" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="12" settings="1">
          <c>(1)</c>
        </box>
        <box hibit="11" width="5" name="imm5" usename="1">
          <c colspan="5"></c>
        </box>
        <box hibit="6" width="2" name="stype" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="4" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_r_A1_RRX" oneofinclass="2" oneof="3" label="Rotate right with extend" bitdiffs="imm5 == 00000 &amp;&amp; stype == 11">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLI" />
          <docvar key="mnemonic-shift-type" value="PLI-rrx" />
          <docvar key="shift-type" value="rrx" />
        </docvars>
        <box hibit="11" width="5" name="imm5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="6" width="2" name="stype">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> , RRX]</text></asmtemplate>
      </encoding>
      <encoding name="PLI_r_A1" oneofinclass="2" oneof="3" label="Shift or rotate by value" bitdiffs="!(imm5 == 00000 &amp;&amp; stype == 11)">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="PLI" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <box hibit="11" width="7" name="imm5:stype">
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>Z</c>
          <c>N</c>
          <c>N</c>
        </box>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field &quot;U&quot;) [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to index register (field &quot;stype&quot;) [ASR,LSL,LSR,ROR]">&lt;shift&gt;</a><text> #</text><a link="sa_amount_1" hover="Shift amount [1-31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) (field &quot;imm5&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_r/A1_A.txt" mylink="aarch32.instrs.PLI_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = (U == '1');
(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);
if m == 15 then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
      <docvars>
        <docvar key="address-form" value="register-offset" />
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
        <docvar key="mnemonic" value="PLI" />
      </docvars>
      <iclassintro count="1"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/PLI_r/T1_A.txt" tworows="1">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="2" name="size" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" settings="1">
          <c>1</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="15" width="4" name="Rt" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" width="2" name="imm2" usename="1">
          <c colspan="2"></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="PLI_r_T1" oneofinclass="1" oneof="3" label="T1">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="PLI" />
        </docvars>
        <asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field &quot;Rm&quot;)">&lt;Rm&gt;</a><text> </text><text>{</text><text>, LSL #</text><a link="sa_amount" hover="Shift amount [0-3], default 0 (field &quot;imm2&quot;)">&lt;amount&gt;</a><text>}</text><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/PLI_r/T1_A.txt" mylink="aarch32.instrs.PLI_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "PLI (immediate, literal)";
n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  add = TRUE;
(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));
if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
        </ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_c_1">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax>&lt;c&gt;</syntax> must be <value>AL</value> or omitted.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="2">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the general-purpose base register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa__plusminus_">+/-</symbol>
      <definition encodedin="U">
        <intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">U</entry>
                <entry class="symbol">+/-</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">-</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">+</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="1">
      <symbol link="sa__plus_">+</symbol>
      <account encodedin="">
        <intro>
          <para>Specifies the index register is added to the base register.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1, PLI_r_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the general-purpose index register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_shift">&lt;shift&gt;</symbol>
      <definition encodedin="stype">
        <intro>Is the type of shift to be applied to the index register, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">stype</entry>
                <entry class="symbol">&lt;shift&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">LSL</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">LSR</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ASR</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">ROR</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="PLI_r_A1" symboldefcount="1">
      <symbol link="sa_amount_1">&lt;amount&gt;</symbol>
      <account encodedin="imm5">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic-shift-type" value="PLI-shift-no-rrx" />
          <docvar key="shift-type" value="shift-no-rrx" />
        </docvars>
        <intro>
          <para>For encoding A1: is the shift amount, in the range 1 to 31 (when &lt;shift&gt; = LSL or ROR) or 1 to 32 (when &lt;shift&gt; = LSR or ASR) encoded in the "imm5" field as &lt;amount&gt; modulo 32.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="PLI_r_T1" symboldefcount="2">
      <symbol link="sa_amount">&lt;amount&gt;</symbol>
      <account encodedin="imm2">
        <docvars>
          <docvar key="address-form" value="register-offset" />
          <docvar key="armarmheading" value="T1" />
          <docvar key="isa" value="T32" />
        </docvars>
        <intro>
          <para>For encoding T1: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/PLI_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
    address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);
    <a link="impl-aarch32.Hint_PreloadInstr.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadInstr(bits(32) address)">Hint_PreloadInstr</a>(address);</pstext>
    </ps>
  </ps_section>
</instructionsection>
