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<instructionsection id="SMLALD" title="SMLALD, SMLALDX -- AArch32" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general" />
  </docvars>
  <heading>SMLALD, SMLALDX</heading>
  <desc>
    <brief>
      <para>Signed Multiply Accumulate Long Dual</para>
    </brief>
    <authored>
      <para>Signed Multiply Accumulate Long Dual performs two signed 16 x 16-bit multiplications. It adds the products to a 64-bit accumulate operand.</para>
      <para>Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top x bottom and bottom x top multiplication.</para>
      <para>Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 2<sup>64</sup>.</para>
    </authored>
    <encodingnotes>
      <para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
    </encodingnotes>
  </desc>
  <operationalnotes>
    <para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
    <list type="unordered">
      <listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
      <listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
    </list>
  </operationalnotes>
  <alias_list howmany="0"></alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from the following instruction sets:</txt>
      <txt> A32 (</txt>
      <a href="#iclass_a1">A1</a>
      <txt>)</txt>
      <txt> and </txt>
      <txt> T32 (</txt>
      <a href="#iclass_t1">T1</a>
      <txt>)</txt>
      <txt>.</txt>
    </classesintro>
    <iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
      <docvars>
        <docvar key="armarmheading" value="A1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="A32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="32" psname="aarch32/instrs/SMLALD/A1_A.txt" tworows="1">
        <box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
          <c colspan="4">!= 1111</c>
        </box>
        <box hibit="27" width="5" settings="5">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="5" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="4" settings="1">
          <c>1</c>
        </box>
        <box hibit="3" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALD_A1" oneofinclass="2" oneof="4" label="SMLALD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALD" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALDX_A1" oneofinclass="2" oneof="4" label="SMLALDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="A1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="A32" />
          <docvar key="mnemonic" value="SMLALDX" />
        </docvars>
        <box hibit="5" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALD/A1_A.txt" mylink="aarch32.instrs.SMLALD.A1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
if dHi == dLo then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="A1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">dHi == dLo</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
    <iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
      <docvars>
        <docvar key="armarmheading" value="T1" />
        <docvar key="instr-class" value="general" />
        <docvar key="isa" value="T32" />
      </docvars>
      <iclassintro count="2"></iclassintro>
      <regdiagram form="16x2" psname="aarch32/instrs/SMLALD/T1_A.txt">
        <box hibit="31" width="9" settings="9">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" width="3" name="op1" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="19" width="4" name="Rn" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="15" width="4" name="RdLo" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="11" width="4" name="RdHi" usename="1">
          <c colspan="4"></c>
        </box>
        <box hibit="7" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" name="M" usename="1">
          <c></c>
        </box>
        <box hibit="3" width="4" name="Rm" usename="1">
          <c colspan="4"></c>
        </box>
      </regdiagram>
      <encoding name="SMLALD_T1" oneofinclass="2" oneof="4" label="SMLALD" bitdiffs="M == 0">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALD" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>0</c>
        </box>
        <asmtemplate><text>SMLALD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="SMLALDX_T1" oneofinclass="2" oneof="4" label="SMLALDX" bitdiffs="M == 1">
        <docvars>
          <docvar key="armarmheading" value="T1" />
          <docvar key="instr-class" value="general" />
          <docvar key="isa" value="T32" />
          <docvar key="mnemonic" value="SMLALDX" />
        </docvars>
        <box hibit="4" width="1" name="M">
          <c>1</c>
        </box>
        <asmtemplate><text>SMLALDX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text> </text><a link="sa_rdlo" hover="General-purpose source register holding lower 32 bits of addend (field &quot;RdLo&quot;)">&lt;RdLo&gt;</a><text>, </text><a link="sa_rdhi" hover="General-purpose source register holding upper 32 bits of addend (field &quot;RdHi&quot;)">&lt;RdHi&gt;</a><text>, </text><a link="sa_rn" hover="First general-purpose source register (field &quot;Rn&quot;)">&lt;Rn&gt;</a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field &quot;Rm&quot;)">&lt;Rm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="aarch32/instrs/SMLALD/T1_A.txt" mylink="aarch32.instrs.SMLALD.T1_A.txt" enclabels="" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">dLo = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdLo);  dHi = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(RdHi);  n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);  m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);  m_swap = (M == '1');
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
// Armv8-A removes UNPREDICTABLE for R13
if dHi == dLo then UNPREDICTABLE;</pstext>
        </ps>
      </ps_section>
      <constrained_unpredictables encoding="T1" ps_block="Decode">
        <cu_case>
          <cu_cause>
            <pstext mayhavelinks="1">dHi == dLo</pstext>
          </cu_cause>
          <cu_type constraint="Constraint_UNDEF" />
          <cu_type constraint="Constraint_NOP" />
          <cu_type constraint="Constraint_UNKNOWN" />
        </cu_case>
      </constrained_unpredictables>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_c">&lt;c&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_q">&lt;q&gt;</symbol>
      <account encodedin="">
        <intro>
          <para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rdlo">&lt;RdLo&gt;</symbol>
      <account encodedin="RdLo">
        <intro>
          <para>Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rdhi">&lt;RdHi&gt;</symbol>
      <account encodedin="RdHi">
        <intro>
          <para>Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rn">&lt;Rn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SMLALD_A1, SMLALD_T1" symboldefcount="1">
      <symbol link="sa_rm">&lt;Rm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="aarch32/instrs/SMLALD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
    EncodingSpecificOperations();
    operand2 = if m_swap then <a link="impl-shared.ROR.2" file="shared_pseudocode.xml" hover="function: bits(N) ROR(bits(N) x, integer shift)">ROR</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],16) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];
    product1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;15:0&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;15:0&gt;);
    product2 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]&lt;31:16&gt;) * <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand2&lt;31:16&gt;);
    result = product1 + product2 + <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dHi]:<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[dLo]);
    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dHi] = result&lt;63:32&gt;;
    <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[dLo] = result&lt;31:0&gt;;</pstext>
    </ps>
  </ps_section>
</instructionsection>
